育才学习网1.请问怎么用VHDL写个程序把频率从50MHz转换成40MHz啊
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PL_ASK is
port(clk : in std_logic;
start : in std_logic;
x : in std_logic;
y1 : out std_logic;
y : out std_logic
);
end;
architecture behav of PL_ASK is
signal q : integer range 0 to 3;
signal f : std_logic;
begin
process(clk)
begin
if clk'event and clk='1' then --分频计数器
if start='0' then
q
2.用VHDL语言编写程序
我用quartusⅡ已编译并且仿真都对的，我写的是0亮1灭，如果实际情况与这相反，你自己倒一下。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
USE IEEE.numeric_std.all;
ENTITY test IS
PORT (clock: in std_logic; -----clock1加48MHz的信号
row: out std_logic_vector(0 to 7));
END test;
ARCHITECTURE behave OF test IS
CONSTANT fp_clka:INTEGER:=12000000； ---扫描信号频率为2Hz
SIGNAL a: INTEGER RANGE 0 TO 12000001;
signal saomiao :integer range 0 to 9;
SIGNAL clka: std_logic;
BEGIN
PROCESS (clock)
BEGIN
IF rising_edge(clock) THEN
IF a<fp_clka then --clka
a<=a+1;
clka<=clka;
ELSE
a<=0;
clka<= NOT clka;
end if;
end if;
end process;
process(clka)
BEGIN
IF rising_edge(clka) THEN
saomiao<=saomiao+1;
if saomiao=9 then
saomiao<=0;
end if;
case saomiao is ---'1'代表不亮，'0'代表亮
when 0 =>row<="01111111";
when 1 =>row<="10111111";
when 2 =>row<="11011111";
when 3 =>row<="11101111";
when 4 =>row<="11110111";
when 5 =>row<="11111011";
when 6 =>row<="11111101";
when 7 =>row<="11111110";
when 8 =>row<="00000000";
when others =>row<="11111111";
END CASE;
END IF;
end process;
END behave;
3.谁知道 怎么用vhdl 写个138
138是三线八线译码器吧，这个我仿真过了，可以用的
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY 74138 IS
PORT(CLK: IN STD_LOGIC;
datain: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
dataout: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY 74138;
ARCHITECTURE bhv OF 74138 IS
BEGIN
PROCESS(CLK,datain)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
CASE datain IS
WHEN "000" => dataout WHEN "001" => dataout WHEN "010" => dataout WHEN "011" => dataout WHEN "100" => dataout WHEN "101" => dataout WHEN "110" => dataout WHEN "111" => dataout WHEN OTHERS =>dataout END CASE;
END IF;
END PROCESS;
END ARCHITECTURE bhv;
4.FPGA十分频程序,用VHDL写
我这个是可以实现多个分频的。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DVF IS
PORT(CLK:IN STD_LOGIC； ----时钟输入---
D:IN STD_LOGIC_VECTOR(7 DOWNTO 0)； ----这个输入11111111-1010=1110101即是十分频----
FOUT:OUT STD_LOGIC）； ----对CLK十分频后的输出----
END;
ARCHITECTURE ONE OF DVF IS
SIGNAL FULL:STD_LOGIC;
SIGNAL F_T:STD_LOGIC;
BEGIN
P_REG:PROCESS(CLK)
VARIABLE CNT8:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF CNT8="11111111"THEN
CNT8:=D;
FULL<='1';
ELSE CNT8:=CNT8+1;
FULL<='0';
END IF;
END IF;
END PROCESS P_REG;
P_DIV:PROCESS(FULL)
VARIABLE CNT2:STD_LOGIC;
BEGIN
IF FULL'EVENT AND FULL='1' THEN
CNT2:=NOT CNT2;
IF CNT2='1' THEN
F_T<='1';
ELSE F_T<='0';
END IF;
END IF;
END PROCESS P_DIV;
FOUT<=F_T;
END;
5.如果是用VHDL语言要怎么写呢
可以参考 xilinx 的 application note "Serial Code Conversion between BCD and Binary" ponent described above.bcdconvtb.vhd This contains a testbench which applies a serial binary input representing a range of binary numbers, and then writes out the corresponding BCD equivalents----------------------------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use STD.textio.all; entity BCDConvTB is end; architecture Bench of BCDConvTB is component BCDConv generic (N : positive); port (Clock : in std_logic; Reset : in std_logic; Init : in std_logic; ModIn : in std_logic; ModOut : out std_logic; Q : out std_logic_vector(N*4-1 downto 0) ); end component; -- hold an array of BCD digits type BCDVectorT is array (natural range <>) of std_logic_vector(3 downto 0); -- number of digits implemented in this test bench constant N : positive := 5; -- BCD array as a single std_logic_vector (packed in 4 bits at a -- time) subtype BcdT is std_logic_vector(N*4-1 downto 0); signal Clock : std_logic; signal Reset : std_logic; signal Init : std_logic; -- Initialise BCD conversion signal ModIn : std_logic; -- modulus in, if we wanted to -- cascade lots of NDigits design entities signal ModOut : std_logic; -- modulus out, same reason as ModIn signal Q : BCDT; -- The outputs of the BCD conversion packed -- into a std_logic_vector -- Test bench control signal to ensure Clock stops when testing is over signal StopClock : boolean; -- Outputs of BCD conversion as an array of 4 bit digits. signal BCDVec : BcdVectorT(1 to N); -- Type to allow a table of test values type TableT is array (natural range <>) of Integer; -- some interesting values to test constant Table : TableT := (17,18,19,20,21,22,23,30,40,50, 60,70,80,90,91,92,93,94,95,96, 97,98,99,100,101,302, 555,707,9999,10100, 99999); signal TestInteger : Integer; begin UUT: BCDConv generic map (N => N) port map ( Clock => Clock, Reset => Reset, Init => Init, ModIn => ModIn, ModOut => ModOut, Q => Q); -- 100 ns clock. Clock loop stops automatically when the -- stimulus process has finished, using the boolean signal StopClock ClockGen: process begin while not StopClock loop Clock <= '0'; wait for 50 ns; Clock <= '1'; wait for 50 ns; end loop; wait; end process;-- -- Generate a set of values to test the Binary to BCD converter -- StimGen: process variable TestVal : BCDT; variable L : LINE; begin Reset <= '0'; ModIn <= '0'; Init <= '0'; wait until falling_edge(Clock); Reset <= '1'; wait until falling_edge(Clock); Reset <= '0';-- test all the values in the table write(L, STRING'("Expected:"), LEFT, 10); write(L, STRING'("Actual:"), LEFT, 10); writeline(OUTPUT,L); for I in Table'RANGE loop -- convert integer value to std_logic_vector TestVal := std_logic_vector(to_unsigned(Table(I), N*4)); -- assign the test value to an integer signal - easy to -- disply in the simulator TestInteger <= Table(I); write(L, Table(I), LEFT, 10); -- Loop round all the bits in the input vector for J in BCDT'RANGE loop -- initialise conversion if shifting 。
转载请注明出处育才学习网 » 怎么用VHDL写变频器
